Program Status Register(PSR)

Overview
Application PSR (APSR)
Execution PSR

Overview

The Cortex-M3 has a special register called “Program Status Register (PSR)” that shows the execution status of the program.Generally, it is installed in microcomputers with a name like Condition Code Register (CCR), but the In Cortex-M3, in addition to the general CCR functions, it is possible to know the execution results of special instructions and the status of interrupts.

The Program Status Register (PSR) represents the system-level processor status and can be divided into three categories

Application PSR (APSR)
Interrupt PSR (IPSR)
Execution PSR (EPSR)

They can be accessed using move instructions (MRS/MSR instructions) between status registers and general-purpose registers, either as individual registers or as a combination of all three.Use the command name xPSR to access them all together.

An example of a description is shown below.

Example 1: APSR

If you want to read only N, Z, C, V and Q of APSR, write as follows. Now, the contents of the APSR are stored in Register 3.
　MRS　 r3 , APSR ;

例2：IPSR

If you want to read only the interrupt number of IPSR, write as follows. Now, the contents of the IPSR are stored in Register 1.
　MRS　 r1 , IPSR ;

例3：xPSR

If you want to read the entire xPSR, write the following Now, the contents of xPSR are stored in register 2.
　MRS　 r2 , PSR ;

PSRs are stored on the stack during exception handling.

Application PSR (APSR)

The following is an explanation of each bit of the APSR.

N is a negative flag. This flag is set to 1 when the result of an operation is “negative” or “less than”.: 1 = The result is “negative” or “less than”; 0 = The result is “positive” or “greater than”
Z is a zero flag. 1 stands when the result of the operation is 0.: 1 = The result is 0.; 0 = The results are not zero.
C is a carry or borough flag. When a carry or a bolo occurs in the result of an operation, 1 stands. C can be calculated together with instructions such as addition and subtraction.: 1 = Carry or borough available; 0 = No carry and borough
V is the overflow flag. When an overflow occurs, 1 stands.: 1 = There is an overflow; 0 = No overflow
Q is a sticky saturation flag. When saturation occurs during a saturation operation, 1 is set to 1.Cortex-M3 has two instructions, SSAT for signed and unsigned saturation operations, and USAT.Refer to the glossary at the end of the chapter for information on saturation operations.

Execution PSR

In “Part 4: Overview of the Instruction Set,” we wrote that”There is not enough space in the encoding space for Thumb 16-bit instructions such as the IT (if then) instruction, so instructions for functions that were not in the Thumb compiler were added in the Thumb-2 instruction.”The execution state of such an instruction is entered in the “Execution PSR”. This register contains two fields, a field shared by ICT/IT and a Thumb state bit.

ICI

Interruptible-Continuable Instruction (ICI) field. Interruptible and post-interruption continuous instructions for interrupted multiple load and multiple store instructions.Load Multiple registers (LDM) and Store Multiple registers (STM) operations can be interrupted, and the ICI field in the EPSR contains the information needed to continue Load Multiple registers or Multiple registers from the point where the interruption occurred.That is, if an interrupt occurs during an LDM or STM transfer, multiple transfers will be interrupted.At this time, the next number of the register that is the operand for multiple transfers is stored in bit [15:12].After the interrupt processing is complete, the processor returns to the register stored in bit [15:12] and resumes the transfer.

Execution state field for the If-Then (IT) instruction.

This contains the number of instructions and execution conditions in the If-Then block.

Thumb state bits (T-bit)

T-bits stand when a 16-bit instruction in the Thumb-2 instruction set is being executed; the Thumb state is a state in which a 16-bit instruction is being executed on a conventional Arm core.The traditional Arm core had 32-bit Arm instructions and 16-bit Thumb instructions.Then, the core had to switch states depending on which instruction it was executing.The state of executing the Arm instruction was called the Arm state, and the state of executing the Thumb instruction was called the Thumb state.

The 16-bit instructions in Cortex-M3 are fully compatible with the Thumb instructions, but there is no distinction between the Arm and Thumb states when viewed by the user.That is, the Thumb-2 instruction set does not need to switch between a fully compatible 16-bit instruction and a new 32-bit instruction state to execute the Thumb instruction.It is completely a mixed instruction set of 16 and 32 bits.

Interrupt PSR

Contains the currently active interrupt handling routine (ISR) number of the exception. The exception numbers are as follows.

base level= 0

NMI = 2

SVCall = 11

INTISR［0］ = 16

INTISR［1］ = 17

：

INTISR［15］ = 31

：

INTISR［239］ = 255

saturation operation

A saturation operation is an operation that fixes (clips) to a specified value when the result of an operation exceeds the specified value.Minimum/maximum clipping prevents variable overflow and reduces CPU load due to software range checking.

It is generally used for signal processing as shown in the figure below.For example, when amplifying an input signal, it is used to reduce the distortion of the signal by saturating it when the output exceeds a specified range.It can also be used for data conversion.It can also be used if you want to convert a 32-bit integer value to a 16-bit integer value.However, since the C compiler may not support the saturation operation instruction, it is necessary to check it. In such a case, you have to write it in assembler.