Features of the memory map
The memory map of the Cortex-M3 has some features that are slightly different from the memory map of a typical microcontroller. The next step is to explain its characteristics.
defined memory map
The memory area of the Cortex-M3 is 4GB in total, since the program counter (PC) is 32 bits.The details of memory mapping are described in “Cortex-M3 memory map” in this page.
Some common microcomputers can change the memory area.However, the memory map of Cortex-M3 is a defined memory map, and the address area mapping is fixed.There are a number of reasons, but the biggest one is that there is a bit-field instruction that prevents the relative relationship between the original address and the alias address from being broken.Fixed address mapping also makes it easier to port between microcomputers with different Cortex-M3s.
No distinction between code area and data area.
Another feature is that there is no distinction between the code area and the data area. Therefore, it is possible to execute code placed on the RAM area.Some microcontrollers have EEPROMs mounted on the RAM area, so code can be executed on EEPROMs as well.
In some general microcomputers, the Flash ROM is divided into a program area and a data area, and programs cannot be written in the data area.Even if you have a large address space, don’t you think it would be a waste if there are restrictions on how you can use it?
With Cortex-M3, there are no such limitations, so users are free to use the address space.
Taking advantage of the fact that programs can also be executed in the RAM area, some products allow programs with small code sizes to be executed by placing the code in RAM or EEPROM and stopping the Flash ROM to optimize current consumption.Of course, at this time, the vector table can also be moved to RAM or EEPROM and interrupts can be accepted.
Easy bit operation
There are bitband areas in the periphery and RAM areas that can easily use bitbands, but not all areas can use bitbands.(See “Cortex-M3 memory map” in this page)
Other features
As we’ve already discussed, unaligned data access (Refer to the eighth).You can also choose Little Endian, Big Endian (see 13th) configurations are available for selection.
MPU (Memory Protection Unit)
The Cortex-M3 has an optional feature called MPU.An option is not an option that microcontroller users can choose, but rather an option that microcontroller vendors can choose to install in their products or not.
The MPU is equipped with the following features.
- Protects user applications from corrupting the memory space used by the OS.
- It allows you to isolate processes and separate data between processing tasks.
- Unexpected memory accesses (e.g., stack corruption) can be detected.
- You can specify the attributes and permissions of the protected area.
And the main features are as follows.
- Up to 8 areas can be protected.
- A memory map can be defined for privileged access.
- A memory management fault can be generated by accessing a memory location that is not defined in the MPU area.
- A memory management fault can occur when accessing a memory location that is not allowed in the MPU area settings.
- Duplication of the MPU area is possible (attribute specification and permission).
Specifically, the following areas can be set
- Program code for privileged programs (e.g., OS kernel and exception handlers)
- program code for a user program
- Data memory (data + stack) for the privileged program in the code area
- Data memory for the user program in the code area (data + stack)
- Data memory for privileges and user programs in other memory areas (e.g., SRAM)
- System device area (usually for privileged access only: NVIC and MPU registers)
In a nutshell, you can define an area of the address map according to the user’s requirements, and even allow or disallow access to it.It is a very useful function if the product specification states that it is equipped with an MPU, so please make use of it.
Memory Map of Cortex-M3
Vendor specific (0.5GB)
It is assigned to enable microcomputer vendors to implement peripherals and compatibility in traditional systems.
Private peripheral bus (1MB)
Address space for system components. (CoreSight, NVIC, etc.)
- Private Peripheral Buses – External
It is used to interface with external tools (ETM, trace, etc.). - Private perimeter bus – internal
It is used for internal interfaces such as data watches and breakpoints.
External device (1GB)
For expansion to an external device or to an external memory that requires an array/non-buffer.
External RAM (1GB)
It is for expansion to external memory.
Surrounding (0.5GB)
The lower 1 MB (0x40000000 – 0x400FFFFF) of the 32 MB of address space for peripherals for normal peripherals is reserved for bit-band access.32 MB of bit-band alias space (0x42000000 – 0x43FFFF) has been allocated to this 1 MB.
SRAM (0.5GB)
Internal SRAM area.The lower 1MB of address space in SRAM (0x20000000 – 0x200FFFFF) is reserved for bit bands.
Access to the 32 MB of SRAM bit-band alias area (0x22000000 – 0x23FFFF) is allocated to this 1 MB.
Code (0.5GB)
It is reserved as a code area (Flash, SRAM).This area is accessed via the Cortex-M3 Icode and Dcode buses.
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