GIC (General Interrupt Controller)

　
Reviewing Arm Processor Interrupts Arm processors (except the Cortex-M series) use IRQ and FIQ interrupts as a general-purpose exception; with two-input interrupts, software handling of multiple interrupt requests from peripherals, depending on their priority, is The responsiveness of interrupts is a concern. To solve this problem, GICs can be used to improve the responsiveness of interrupt handling.

Generic Interrupt Controller Architecture（GIC-390）
・Cortex-A9 MPCore
・Cortex-A5 MPCore
Generic Interrupt Controller Architecture（GIC-400）
・Cortex-A15 MPCore
・Cortex-A7 MPCore

Overview of the GIC
Introject handler using GIC

Overview of the GIC

Unlike the NVIC (Integrated Nested Vector Interrupt Controller) in the Cortex-M series, the GIC can execute interrupt handlers directly by addressing interrupts that occur in the interrupt handler in an exception table. The interrupt ID number occurring on the “1” is acquired from the register and executed in software.

GICブロック図

Multiple interrupts from peripheral circuits are connected to the GIC to control the processor’s IRQ/FIQ pin; when an IRQ interrupt occurs, the GIC’s ICCIAR (interrupt acknowledge register) can be read with the interrupt ID number with the highest priority, and the interrupts can be read according to that number. Processing. At the end of an interrupt, the contents of the ICCIAR (interrupt acknowledge register) are written to the ICCOIR (interrupt end register).

Interrupt ID number

When using GIC, it consists of three different functions.

Name	Features	ID
SGI	Software Generation Interrupt0-15	An interrupt can be generated between processors by writing to the ICDSGIR (Software Generated Interrupt Register). The processor that generates the interrupt can be selected.
PPI	Private Peripheral Interrupts16-31	Available on the relevant processor. ID27: Global Timer ID28: nFIQ (Legacy FIQ signal) ID29: Private timers ID30: Private Watchdog ID31: nIRQ (Legacy IRQ Signal)
SPI	Shared Peripheral Interrupts254	The interrupt can be identified from any core; the interrupt occurs on the processor selected by ICDIPTRn (Interrupt Processor Target Register).

interrupt priority

The GIC has an 8-bit priority field, with 32 levels of priority for secure state and 16 levels of priority for non-secure state. (For more information on secure state and non-secure state, see Part 15: TrustZone (Security Extensions).

合わせて読みたい

TrustZone（セキュリティ拡張機能）
2015.05.30

The interrupt mask is set by ICCPMR (priority mask register), the interrupt priority field of GIC is implemented from the upper side, and in the case of 32 levels of priority, it is set by Bit7 to Bit3 and Bit2 to Bit0 will be 0.

【ICCPMR (priority mask register)】

【ICCPMR (Interrupt Priority Register) setting sample program】

ICCPMR_OFFSET EQU 0x0104 ; ICCPMR (priority mask register) offset definition
;
; Functional form: void gicc_set_priority_mask(unsigned int priority)
priority is set on a scale from 0 to 31.
gicc_set_priority_mask
     MRC p15,4,r1,c15,c0,0 ; Read the first address of the private memory space.
     AND r0,r0,#0x1F ; Mask at the interrupt setting level
     MOV r0,r0,LSL #3 ; Set the mask setting to higher level.
     STR r0,[r1,#ICCPMR_OFFSET] ; Write to the Priority Mask register.
     BX lr

Register Placement Address

The control registers that use the GIC are located in private memory space. The “Interrupt Controller” and “Interrupt Distributor” registers must be set up. The top address of the private memory space reads the configuration base address register of the coprocessor 15.

【List of registers placed in private space】
Offset Addresses	Peripheral name
0x0000	Snoop Control Unit
0x0100	Interrupt Controller
0x0200	Global Timer
0x0600	Private Timers and Watch Docks
0x1000	Interrupt splitter

【Register Access Instructions】

MRC p15,4,<Rt>,c15,c0,0; read the configuration base address register
MCR p15,4,<Rt>,c15,c0,0; Writing to the configuration base address register

GIC Initialization

The GIC consists of an interrupt controller and an interrupt splitter, which are stopped at reset and must be set to the operating status.

ICDISERn (interrupt enable set register)

When using interrupts, the interrupt ID number used for the ISDERn must be set to allow interrupts. 224 interrupts) are placed at offset addresses 0x1100 to 0x111C from the top of the private memory space.

ICDIPRn (interrupt priority register)

The priority of the interrupt must be set in 8-bit increments to ICDIPTRn, which is located at offset addresses 0x1400 to 0x14FC from the beginning of the private memory space.

ICDIPTRn (interrupt processor target register)

When using SPI (Shared Peripheral Interrupts), the processor for interrupt processing can be selected. The selection of the processor must be set to ICDIPTRn, which is set in 8-bit increments, but the lower 4 bits are enabled; ICDIPTRn is located at offset addresses 0x1800 to 0x18FC from the beginning of the private memory space.

Processor selection can be selected on a per-bit basis.

Select Bit0/Bit8/Bit16/Bit24 =CPU0
Bit1/Bit9/Bit17/Bit25 = select CPU1
Select Bit2/Bit10/Bit17/Bit25=CPU2
Select Bit3/Bit11/Bit18/Bit26=CPU3

SGI[15:0] and PPI[15:0] cannot be set.

ICCICR (CPU Interface Control Register)

Enables an interrupt signal to the target processor.

ICDDCR (Distributor Control Register)

Allows forwarding of pending interrupts to the CPU interface.

【Register format of ICCICR/ICDDCR】

Introject handler using GIC

The IRQ interrupt handler performs saving and returning of registers to the stack and return address correction. For the interrupt handler, use the “7th: Exceptions and Interrupts“.

【IRQ Interrupt Handler Example】

IRQ_Handler
    PUSH {r0-r3,r12,lr} ; Save registers on the stack
    BL irq_execution ; Interrupt processing function for interrupt controller
    POP {r0-r3,r12,lr} ; Return a register from the stack
    SUBS pc,lr,#4 ; return address correction and return from exception handling

【Example Description of Interrupt Processing Functions for an Interrupt Controller】

When ICCIAR is read, it returns the interrupt ID of the highest priority among the pending state interrupts.
Execute the corresponding interrupt processing function from the interrupt ID.

ICCEOIR lights the content of ICCIAR.

The GIC manages the state of the interrupt in the following states.

Inactive: no interrupt is requested

Pending: an interrupt has been requested but not accepted by the processor

Active: the processor is accepting interrupts

void irq_execution(void)
{
     int irq_req,irq_no;

     // Reads the ICCIAR
     irq_req = gicc_get_interrupt_acknowledge();
    // Request an interrupt ID number.
     irq_no = irq_req & 0x3ff;
     switch(irq_no){
      // Add an interrupt processing function for each interrupt ID number.
     }
     // Light on ICCEOIR
     gicc_set_end_interrupt(irq_req);
}

ICCIAR (interrupt acknowledge register)

The interrupt ID number with the highest priority in pending state interrupts is set to the interrupt ID number, and the CPU ID number is set to 0 except for SGI (software generated interrupt).

ICCEOIR (interrupt end register)

By writing the contents of ICCIAR, the interrupt process is completed.

【Register Formats for ICCIAR/ICCEOIR】

References

To learn how to use the GIC, we recommend the following three manuals

Generic Interrupt Controller(PL390) Technical Reference Manual

Arm Generic Interrupt Controller Architecture Specification

Cortex-A9 MPCore Revision: r4p1 Technical Reference Manual

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