Overview of the Cortex-M3 processor
Here’s a brief overview of the Cortex-M3 processor’s features After that, I’d like to explain each feature in detail.
Features of the Cortex-M3 core
The Cortex-M3 core is a low-power core that features fewer gates, short interrupt overhead, and low cost of debugging.It is suitable for embedded applications that require a fast interrupt response function.
Thumb-2 instruction set
The Cortex-M3 core uses the Thumb-2 instruction set (mixed 16-bit and 32-bit length instructions).This is a subset of the Instruction Set Architecture (ISA), which is a All 16- and 32-bit basic Thumb-2 Harvard architecture instructions are included, but Media, single instruction multiple data (SIMD), digital signal processing (DSP) instructions (E variant), and Arm system access portions are not included (the Cortex-M4 is included).And it offers both the performance of 32-bit code and the high code density of 16 bits. (Arm instructions such as Arm7 cannot be used.)
By adopting the Harvard architecture, the instruction and data buses are configured independently, allowing efficient memory access.For example, instruction fetch and data storage can be performed simultaneously.
The vector table is not an instruction method but an address method. It is a simple method that only needs to store the jump destination address.
Full C language support
It is fully compatible with C language. It is possible to write exception handling resets and interrupts in C.
It is a three-stage pipeline of fetch, decode, and execution.
Integrated System Timer (SysTick)
Real-time operating system, integrated system timer (SysTick) for scheduled tasks. Easily manage your time base.
Hardware division (divider)
There are hardware division instructions SDIV and UDIV (Thumb-2 instruction, signed and unsigned division).It runs for 2 to 12 cycles.The number of cycles depends on the dividend and divisor,If the dividend and divisor are about the same size, division ends in a small number of cycles.In addition, division is interrupted by interruptions.In that case, the operation result is discarded once and recalculated.
Integrated Bus Matrix Bus Interface
Since it uses integrated bus matrices, it has features such as bus arbiters, bit banding for easy bit manipulation, and write buffers to buffer write data.
Multiplication of a 32-bit result takes one cycle, while multiplication of a 64-bit result takes three to seven cycles.A mechanism is used to terminate operations faster depending on the source value.Also, just like division, multiplication is interrupted when an interruption occurs during execution.
|16b x 16b||32b||1|
|32b x 16b||32b||1|
|32b x 32b||32b||1|
|32b x 32b||64b||3-7|
Nested Vectored Interrupt Controller(NVIC)
The Nested Vectored Interrupt Controller (NVIC) is tightly integrated into the processor, allowing for short overhead interrupt handling.
External interrupts (not external interrupts in the microcontroller but as CPU cores) can be from 1 to 239 factors.The priority can be selected between 3 and 8 bits (up to 256 levels).Since the priority of interrupts can be set dynamically, the priority can be changed to control the order in which interrupts are executed, even in interrupt service routines.
In addition, it is possible to group priorities.This allows the user to select the level of interrupts that are to be executed in priority and the level of interrupts that are not to be executed.In interrupt processing, the state between interrupts is saved and restored (PUSH &POP)This allows for continuous interrupt processing without the overhead of.There is no instruction overhead because the processor state is automatically saved on interrupt entry and restored on interrupt return.To reduce the overhead of interrupts, it has multiple transfer instructions (LDM/STM), PUSH/POP, which are interruptable and can be continued after an interrupt recovery.
Memory Protection Unit(MPU)
This is an optional MPU used for memory protection.It supports eight memory areas.Sub Region Disable (SRD) enables efficient use of memory space. It is possible to give a default memory map attribute by allowing a background area.
Low-cost debug solution
The Cortex-M3 debugging hardware is based on CoreSight and includes the features listed in the table below.More information about CoreSight can be found on the Arm website.
|function||CoreSight Components||Cortex-M0 (reference)||Cortex-M3|
|Debug|| Debug Interface Technology|
Serial Wire Debug Port (SW-DP) for high performance debugging with few wires and Debug access by one or both of Serial Wire JTAG Debug Port (SWJ-DP) is possible.
|JTAG or Serial Wire Debug (using a Cortex-M0 DAP) Dual mode requires a full CoreSight DAP||Dual JTAG & SWD support (with CoreSight SWJ-DP)|
|Memory access during code execution|
Debug access is available to all of the system’s memory and registers.Access is possible while the core is running, holding, or resetting in all cases.The registers include the Cortex-M3 register bank.
The Flash Patch and Breakpoint (FPB) unit enables patches to breakpoints and code.
|4||6 instruction addresses + 2 literal addresses|
The Data Watchpoint and Trace (DWT) unit enables watchpoints, data tracing, and system profiling.
|trace||ETM Instruction Trace|
Embedded Tracing A macro cell (ETM) can be used to trace instructions in real time.
|Data Watchpoint and Trace(DWT)||—||○(Option)|
|ITM (Instrumentation Trace Macrocell) supports printf-style debugging.||—||○(Option)|
|Interface to AHB trace macrocell||—||○(Option)|
|Serial Wire Viewer||—||○(When there’s a trace.)|
The Trace Port Interface Unit (TPIU) serves as the bridge to the Trace Port Analyzer (TPA).
|—||For M3 TPIU, 1 to 4 bits.|
Larger trace ports are available with CoreSight TPIU
- Of the registers, only the stack pointer (SP) is bank-switching type.
- Handler mode and thread mode
- Thumb state and debug state
- Endian supports BE8/LE in the Armv6 architecture
- Memory access supports Armv6 unaligned access