To enable the SysTick feature, use the SysTick control and status registers.When the ENABLE bit of this register is set to 1, the counter begins to operate.In other words, the counter is loaded with a reload value and then the countdown starts.
The memory map of the Cortex-M3 has some features that are slightly different from the memory map of a typical microcontroller.Some common microcomputers can change the memory area.However, the memory map of Cortex-M3 is a defined memory map, and the address area mapping is fixed.
The vector table in Cortex-M3 starts at number 0.In a typical microcontroller, the minimum address part (0) of the vector table is assigned a reset vector, but in Cortex-M3, the initial value of the main stack (SP_main) is assigned.
This section describes the control registers that the NVIC (Nested Vectored Interrupt Controller) has.SysTick-related registers are also included in NVIC registers, which are described in more detail in the SysTick chapter.
If you read the Cortex-M3 manual, you'll see the words tail-chain, sidestep, and rear-end.This word indicates the timing of exception handling that occurs according to the exception handling priority.A brief explanation of the meaning of each is as follows.
Types of exceptions include resets, interrupts, and faults.The exception handling occurs suddenly. Therefore, it happens asynchronously to the execution of the instruction.However, since only faults are exceptions due to the execution of error conditions due to instruction execution, they basically occur in synchronization with the instruction that caused them.
In Cortex-M3, the endian setting pin BIGEND (Note: It is not a microcontroller pin. (this is the name of the signal line to and from the outside of the logic module).This allows you to choose either the Little Endian or Big Endian format.
The Cortex-M3 has a special register called "Program Status Register (PSR)" that shows the execution status of the program as a special register.The Program Status Register (PSR) represents the system-level processor status and can be divided into three categories