FPU: A pipeline optimized for single precision (SP).The interior is physically divided into two pipelines: one is a simple arithmetic pipeline for addition, etc., and the other is an arithmetic pipeline for multiplication, division, etc.
The process of a superscalar pipeline can be broadly divided into the first half of the process from instruction fetching to instruction decoding (Decode) and instruction issuance (Issue), and the second half of instruction execution.The first half is called the instruction issuance pipeline and the second half is called the instruction execution pipeline.
The Cortex-M7, like the Cortex-M3/M4, features NVIC: Nested Vectored Interrupt Controller, which is the same as the Cortex-M3/M4.Interrupt handling has been optimized for low overhead and interrupt performance.
It's a dual superscara, so there are two ALU.It fetches the code in 64bit, decodes two instructions simultaneously, and issues the decoded results to two ALU.And run it simultaneously.Therefore, as mentioned above, both CoreMark and DMIPS have almost twice the computing power of Cortex-M4.
The Cortex-M7 is an extreme improvement in performance, with a six-stage pipeline and even more dual superscalar construction.CoreMark/MHz has improved from 3.4 on the Cortex-M4 to 5.04 on the Cortex-M7, and DMIPS/MHz has also improved from 1.25 to 2.14.