Memory Interface Overview
As mentioned in the chapter on memory maps, the Cortex-M7 has a variety of bus interfaces: AXIM, ITCM, DTCM, AHBP, and EPPB. Each memory area is then optimized according to the type of memory connected to it and its use. The table below summarizes the interface of the Cortex-M7.
|memory type||memory interface|
|High speed, built-in SRAM||DTCM|
|Slow access time around the built-in||AHBP|
|Slow Flash or off-chip instruction memory||AXIM (via instruction cache)|
|Slow or off-chip data memory||AXIM (via data cache)|
|low-speed peripheral function||AXIM|
|low-speed peripheral function||Buses around APB|
TCM (Tightly Coupled Memory) interface
There are two types of TCM: ITCM for instruction access and DTCM for data access. Both provide support for the weight cycle. In other words, it is optimized for low-speed memory. It is also made available for boot up.
The data width of ITCM is double-word 64 bits, and DTCM is 32 bits for D1TCM and D0TCM respectively. The top word accesses D1TCM and the bottom word accesses D0TCM.
The base address is determined and is the following address (see Part 2).
Both TCMs can be used for instruction execution and data access, but the highest performance is achieved by fetching instructions from the ITCM and fetching data from the DTCM.
The ITCM has one 64-bit memory interface, the DTCM, D0TCM, and D1TCM each have a 32-bit memory interface and are selected by the address bit .It is designed to connect RAM or RAM-like memory (common memory). In other words, it is a memory bus that repeatedly writes and reads. It is not suitable for read-only bus or write-only bus. For example, it is not suitable for FIFO read-only bus or write-only bus.
The prefetch unit (PFU) can read the data using the TCM interface. The load/store unit (LSU) and AHBS interface can also read and write data using the TCM interface.
TCM always works as a normal memory in cache-free occupancy. The TCM itself does not have ECC (error checking and correction), but if the memory connected to the TCM supports ECC, the access must be retry to get the corrected data back.
Arbitration of the TCM
TCM is accessed from LSU (for SW loading), PFU (for instruction fetch), and AHBS (for reading AHBS), but their priority is determined. The highest priority is LSU. PFU is next.The AHBS interface has the lowest priority. When a higher priority function is accessing the TCM, the lower priority function will be stalled.
Configuration of ITCM and D0TCM and D1TCM
TCM sizes can be selected from 0KB, 4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, 8MB, and 16MB.The DTCM has two interfaces, D0TCM and D1TCM. This means that the individual interfaces to the RAM have been attached. The size of each is half the size of the entire DTCM.
The instruction/data TCM control register configuration is shown below. (The configuration of “ITCMCR – 0xE000EF90(R/W)” and “DTCMCR – 0xE000EF94(R/W)” is the same).
Overview of AHBS (AHB Slave)
The 32-bit AHB Slave (AHBS) interface provides system access to the ITCM, D1TCM, and D0TCM.Slave interface for the AMBA 3 AHB-Lite protocol.It supports simultaneous system and processor access requests.Writes are buffered by the processor store queue (SQ), which also buffers software writes to the TCM. All stores are in-order (in order) and will not be merged. It can be used even when the processor is in a sleep state.
Restrictions on AHBS transactions
The processor does not support AHBS transactions that rely directly on software memory transactions.This means that the system will not be able to access memory in the software until the AHBS transaction is over.Therefore, looping back from the processor master port to AHBS (returning data to itself) can cause a deadlock, so looping back from the processor master port is not supported.
An AHBS interface transaction cannot perform an MPU lookup. And no distinction is made internally between unprivileged (user mode) and privileged (supervisor mode) AHBS interface access. Therefore, the protection function must be managed by the system.The AHBS interface is accessed according to the requirements of the system.
There is a write buffer for AHBS and the software store that is shared with TCM. This buffer allows for consistency between the software for TCM and AHBS.Writes on the AHBS interface are buffered and always return a speculative (undetermined) OK response. If the write is subsequently aborted, AHBS will abort the write asynchronously.
AHBS does not support exclusive or locked access. The AHBS interface store has no effect on the status of the internal occupied access monitor. Therefore, it is not suitable for systems that require parallelism between the AHBS interface and the software.
Arbitration of AHBS
- There are two points of interest in processor arbitration
- ● Accept writing to SQ for software and AHBS
- ● Execute a TCM read request for software and AHBS
The method of arbitration in these two cases is, in both cases, a round-robin method. If there is no simultaneous request for bus rights, the bus master who requested the bus rights gets the bus rights, but if contention (simultaneous request for bus rights) occurs, the fairness counter mediates the bus rights.
The fairness counter method can guarantee the optimal throughput for the bus master when too much contention occurs, and the optimal average throughput for all bus masters when contention does occur.
- The fairness counter supports five software-configurable arbitration modes
- ● Round robin only.
- ● Round robin using a fairness counter with reduced AHBS interface bandwidth.
- ● Round robin using a fairness counter with reduced software bandwidth.
- ● A reduced AHBS interface round-robin using a fairness counter with execution priority set at the thresholds defined above.
- ● The system controls the AHBS interface bandwidth.
The fairness counter is 4 bits wide.Counters are assigned to software or AHBS to de-prioritize access to the TCM.In the case of contention (multiple people requesting access rights at the same time), when the counter is 0, the assigned master gets arbitration rights. When the counter is not 0, the other master gets the bus right.With each contention, the counter is decremented from 0 to the initial value.The hardware supports the use of counters only for certain priority levels (exception priority).
AHB Slave Control Register
The fairness counter is set by the AHB SCR (AHB slave control register). The details are shown below.
|[15:11]||INTCOUNT||RW||Initial value of the fairness counter.This is used to lower the access priority of the bus right request master selected by AHBSCR.CTL.|
|[10:2]||TRPI||RW||Threshold for lowering the execution priority of AHBS|
0b0xxxxxxx: Priority is TRPI[7:0], same as NVIC encoding.
|[1:0]||CTL||RW||AHB Priority Control|
0b00: AHBS access priority drops
0b01: SW’s access priority goes down.
0b10: AHBS access priority is lowered (if the priority of software execution is greater than or equal to AHBSCR.TRI) or equal access priority is lowered.
0b11: The AHBSPRI signal has access priority control.
AHB Peripheral Interface
The AHBP interface conforms to the 32-bit AHB-Lite interface specification.The 32-bit AHB-Lite interface is the same as the bus specification (S-Bus) for the peripheral functions used in the conventional Cortex-M3 and M4, so the peripheral functions used in the Cortex-M3 and M4 can be connected to the AHBP.AHB slaves connected to the AHBP interface can also process any transaction, except in special cases, as long as it conforms to the AHB specification.
The AHBP interface is subject to the following limitations
- The interface is a one-time transfer. Therefore, every burst is one.
- All transactions do not straddle a four-byte boundary of memory.
- Since it is a 32-bit AHB-Lite interface, the maximum transfer size is 32 bits.
- It only supports data access. Instruction fetching is not possible.
- Transactions to the Device and Strongly-ordered memory are always aligned to the address of the transfer size.
- Exclusive access is always aligned with the address of the transfer size.
AHBP Exclusive Access
The peripheral interface uses the memory system’s internal exclusive monitor to execute the unshared memory load/store/clear exclusive instructions.Internal monitors check for exclusive access to the shared memory and, if necessary, external monitors using the AHB memory interface.Exclusive instructions can be used to guarantee semaphores and synchronization between different processors.
Only an exclusive instruction to the shared memory can (consequently) provide exclusive access to the AHBP.Exclusive access to unshared memory is marked as non-exclusive access on the bus.
Inside the core, the AHBP extension signals (internal signals) EXREQP and EXRESPP signals convey the exclusive request and response for AHBP’s shared proprietary transactions.EXREQP is an address phase signal, EXRESPP is a data phase signal, and the EXREQP signal is asserted in the following cases
- An exclusive load/store is performed on the AHBP and in shared memory on the internal exclusive access monitor path.
Because the Cortex-M7 processor uses EXREQP and EXRESPP differently than the Cortex-M3 and Cortex-M4 processors, systems using the Cortex-M7 processor will need to update the system hardware and software.
AHBP Control Register
The following figure shows the specifications of the AHBPCR (AHBP control register).
Strongly Ordered：A memory type that executes Load and Store in the order in which it is written in the program.
Device：The type with side effects from executing Load and Store. Don’t run speculative or repeat the same behavior.
Normal：Normal memory type. If you read it multiple times the value is the same, if you write the same value multiple times the result is the same.
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