interrupt priority register
In Cortex-M3, the priority of each interrupt can be changed by the user.It can also be set to 256 levels instead of 8 or 16 levels. The interrupt priority register is used for the setting.By setting the PRI_N field (where N stands for interrupt number) in this register, each interrupt can be assigned to a priority order of 0 to 255 on a scale of 256.In this case, the interrupt assigned to 0 has the highest priority and the interrupt assigned to 255 has the lowest priority.
You can also set up two levels of priority.First, it is possible to prioritize it largely by the “usurpation priority (group priority)” priority, and then, within that, it is possible to set the priority.This is called a “sub-priority”; the combination of usurpation priority and sub-priority is commonly referred to as a priority.
PRIGROUP field of the Application Interrupt and Reset Control Register
The PRIGROUP field of the application interrupt and reset control register determines the level of the “usurpation priority” and “sub-priority”.The PRIGROUP field is used to split the values of all PRI_N fields in the priority register into intersection priority and sub-priority fields.Then, the priority is set by the number of bits in the interrupt priority field and the sub-priority field of the PRI_N field of the interrupt priority register.
For example, set the PRIGROUP field to 4.At this time, 3 bits of the MSB side of the PRI_N field are assigned to the usurpation priority and 5 bits of the LSB side of the PRI_N field are assigned to the sub-priority.The usurpation priority is 3 bits, so there are 8 levels of the third power of 2, and the sub-priority is 5 bits, so there are 32 levels.The priority is assigned to a total of 256 levels with 8 levels x 32 levels.
The PRIGROUP field applies to all PRI_N fields, so different PRI_N fields (e.g., PRI_237 and PRI_236) cannot be set to different priorities.(For example, PRI_236 cannot be assigned a PRIGROUP field of 4, and PRI_237 cannot be assigned a PRIGROUP field of 3, etc.)
- PRIGROUP[2:0]＝0 7.1 : 7-bit usurpation priority, 1-bit sub-priority
- PRIGROUP[2:0]＝1 6.2 : 6-bit usurpation priority, 2-bit sub-priority
- PRIGROUP[2:0]＝2 5.3 : 5-bit usurpation priority, 3-bit sub-priority
- PRIGROUP[2:0]＝3 4.4 : 4-bit usurpation priority, 4-bit sub-priority
- PRIGROUP[2:0]＝4 3.5 : 3-bit usurpation priority, 5-bit sub-priority
- PRIGROUP[2:0]＝5 2.6 : 2-bit usurpation priority, 6-bit sub-priority
- PRIGROUP[2:0]＝6 1.7 : 1-bit usurpation priority, 7-bit sub-priority
- PRIGROUP[2:0]＝7 0.8 : No usurpation priority, 2-bit sub-priority
PRI_N Field of the Interrupt Priority Register
There are two interrupt priority registers.These are the priority registers for external interrupts and system handlers of the Cortex-M3.The priority register for external interrupts is 0xE000E400 to 0xE000E4EF. It is possible to read/write.The state at reset is 0x00000000. The priority registers for the system handlers are 0xE000ED18 to 0xE000ED23. It is possible to read/write.The state at reset is 0x00000000.
N in the PRI_N field of the external interrupt priority register corresponds to an external interrupt number.For example, the PRI_0 field is applied to external interrupt #0, and the PRI_1 field is applied to external interrupt #1.
The priority register for the system handlers is used to prioritize the following system handlers.
- Memory Management (PRI_4)
- Bus fault (PRI_5)
- Dosage Fault (PRI_6)
- SVC (PRI_11)
- Debugging Monitor (PRI_12)
- PendSV (PRI_14)
- SysTick (PRI_15)
The N in the PRI_N field also includes reservations for interrupt numbers 7 through 10 and 13.
Prioritization of actual microcontroller products
The usurpation priority and sub-priority levels of the PRIGROUP field of the application interrupt and reset control register are summarized in the table below.
|Usurpation priority (group priority)||sub priority|
In practice, however, it is rare to use 256 levels of interrupt priority.Therefore, actual microcontroller products rarely implement the full 8-bit PRIGROUP[2:0]=0 to 7.For example, there are products that use only 4 bits of the 8-bit interrupt priority.If it is 4 bits, it is executed with 16 levels of priority.
Table 2 shows the interrupt prioritization in the 4-bit case.In this case, of the 8 bits of the PRI_N field of the interrupt priority register, only 4 bits on the MSB side are implemented, so the 4 bits on the LSB side are always read as 0.Please refer to the manual of each product as the actual implementation specification is different for each product.
|Usurpation priority (group priority)||sub priority|
Other prioritization features
The Cortex-M3 has an interrupt mask register with a special role.PRIMASK, FAULTMASK and BASEPRI. These mask registers are accessed by the MRS and MSR instructions.
Setting this bit raises the execution priority to 0.In other words, all interrupts other than NMI and hard faults are disabled.The default value is 0 (no mask is set).
Setting this bit raises the execution priority to -1.In other words, all interrupts other than NMI are disabled.In other words, it is the same as PRIMASK except that the fault handling by the hard fault handler is disabled.The default value is 0 (no mask is set).It is automatically cleared by exiting the exception handler.
All low-priority interrupts with a specific priority N (lowest configurable priority) or less than N are disallowed.N is dependent on the number of bits implemented in each microcontroller product. The maximum is 9 bits.A non-zero value acts as a priority mask.This affects the execution priority when the priority defined by it is the same or higher than the priority currently being executed. The default value is N=0 (mask function is disabled).
PRIMASK and BASEPRI are useful when temporarily disabling an interrupt.FAULTMASK is useful for temporarily disabling fault handling.RIMASK and FAULTMASK cannot be set in the unprivileged access (user access) state.
These mechanisms affect only the usurpation priority (group priority). It does not affect the sub-priority.The sub-priority is only used to classify the exception priority for pending and does not affect active exceptions.