Memory types and access order needs
In this article, we will discuss “Memory Types and Access Orders” as a basic knowledge about memory. In a processor, all instructions are executed in program order, with each instruction completing completely before the next one is started. To increase execution speed, modern processors include instruction completion swapping and caching features, and compilers are optimized to increase processor execution speed. These may cause memory accesses not to occur in the order in which the program is instructed. Understanding this behavior requires knowledge of “memory types”, “access orders” and “C/C++ compiler optimization”.
When using a DMA controller to transfer variables located in RAM to a communication controller, the following steps are used to transfer data in memory.
- Writing of transfer data to RAM (normal memory).
- After writing to the registers of the DMA controller (device memory), DMA transfer is started.
For a successful DMA transfer, it is assumed that the writing of the transfer data on RAM (normal memory) is completed before the DMA controller (device memory) is started. The memory type and access order defines the following behavior.
The access order between normal and device memory is not specified.
Understanding this issue requires an understanding of “memory types” and “access orders” and the use of barrier instructions (see Part 11) to protect the access order.
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memory type
Arm processors define three types of memory and must be configured for different applications. Memory type settings are defined in MMU (for Cortex-A series) and MPU (for Cortex-R series).
| No | Memory Type | Content |
|---|---|---|
| 1 | Normal Memory | Places functions and variables (including structures) created in C/C++ programs. You can use the cache. |
| 2 | Device Memory | Places peripherals (UART/GPIO etc.). Write buffers can be used, but caches are not available. |
| 3 | Strong Acorn Order Memory | Write buffers and caches are unavailable. |
Access order
Cortex-A processors may not guarantee the order of accesses, depending on the memory type. if you execute an LDR or STR instruction, a “0” in the Access Order List guarantees that Addr1 will complete first.
LDR/STR r1,[r0] ; The r0 register is set to the Addr1 address. LDR/STR r3,[r2] ; The r2 register is set to the Addr2 address.
- The “LDR r1,[r0]” instruction reads 32-bit data from the address indicated in the r0 register and reads it into the r1 register.
- The STR r1,[r0] instruction writes 32-bit data in the r1 register to the address indicated in the r0 register.
The caveat here is that access order is guaranteed when placed on devices and strong orders, but access order between normal and device or strong orders is not guaranteed. When placed on a device, access order is not guaranteed between shared and unshared devices
【Access Order List】
Addr1/Addr2 does not overlap, indicating access to different addresses. Because the load/store instructions for the same address range are completed in the program order, the normal operation of the code is guaranteed. For example, the STRD instruction (a 64-bit store instruction) from address 0x2000 will access the range of addresses from 0x2000 to 0x2007.
Since the STRB and LDRH instructions are contained within the 0x2000 to 0x2007 range, the load/store instructions are completed in programmatic order: the STRB instruction is an 8-bit store instruction and the LDRH instruction is a 16-bit load instruction.
Optimizing C/C++ Compiler
The C/C++ compiler optimizes your program to increase the code density. However, it must use the volatile attribute because the optimization may remove some necessary memory accesses.
volatile attribute
The volatile attribute is a reserved term (const, volatile, restrict) that assigns a specific attribute to the treatment of data. volatile attributes are either objects that correspond to input and output ports allocated in memory or are accessed by an asynchronous interrupt mechanism Operations on objects declared in the volatile attribute are not removed or reordered by optimization of the processor, except as allowed by the rules for evaluating expressions. For more information, see JIS standard (No. X 3010/Information technology – Programming languages – C).
Example of not setting the volatile attribute
If you do not set the volatile attribute in the definition of PORT3 register and the result of reading PORT3 register twice is the same, you can check the operation of the program that executes the following process.
#define PORT3 (*(unsigned long *)0x40000000) // Port 3 register
while(1){
if( PORT3==PORT3 ){ // Two consecutive reads and a match?
break;
}
}
Example of Assembler Instruction Expansion]
Read PORT3 register once by “LDR r0,[r0]” command, and compare the same value.
LDR r0,=0x40000000 ; Set the address of the PORT3 register. LDR r0,[r0] ; Reads the PORT3 register. CMP r0,r0 ; compare read results BNE ...
Example of setting the volatile attribute
If the definition of PORT3 register is set to volatile attribute and the result of reading PORT3 register twice is the same, the operation of the program that executes the next process is checked.
#define PORT3 (*(volatile unsigned long *)0x40000000) // Port 3 register
while(1){
if( PORT3==PORT3 ){
break;
}
}
Example of Assembler Instruction Expansion]
You can confirm that it works correctly by reading the PORT3 register twice with the “LDR r0,[r0]” and “LDR r1,[r1]” instructions.
LDR r0,=0x40000000 ; Set the address of the PORT3 register. LDR r0,[r0] ; Reads the PORT3 register. LDR r1,=0x40000000 ; Set the address of the PORT3 register. LDR r1,[r1] ; Reads the PORT3 register. CMP r0,r1 ; compare read results BNE …
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