This chapter describes the control registers that the NVIC (Nested Vectored Interrupt Controller) has.SysTick-related registers are also included in NVIC registers, which are described in more detail in “Part 20: SysTick, Power Management “.
Description of each register
interrupt enable set register
The interrupt enable set register is used for “allowing interrupts” and “determining the currently allowed interrupts.Each bit corresponds to one of the 32 interrupts, and the corresponding bit is set to allow the interrupt.
interrupt enable clear register
The interrupt enable clear register is used for disabling interrupts and identifying currently disabling interrupts.Each bit corresponds to one of the 32 interrupts, and setting the corresponding bit disables the interrupt.
interrupt hold set register
The interrupt hold set register is used to hold interrupts and to determine the currently pending interrupt.Each bit corresponds to one of the 32 interrupts and the corresponding bit is set so that the interrupt is put on hold.
interrupt hold clear register
The interrupt pending clear register is used to clear pending interrupts and to determine the currently pending interrupt.Each bit corresponds to one of the 32 interrupts and the corresponding bit is set so that the pending interrupt is inactive.
active bit register
The active bit register can be read out to determine the active interrupt.Each flag in the register corresponds to one of the 32 interrupts.
interrupt controller type register
Read the Interrupt Controller Type Register to find out how many interrupt lines are supported by the NVIC.
CPU ID based registers
The CPU ID base register contains the “core ID number”, “core version number”, and “core implementation details”.
interrupt control state register
The interrupt control state register is used to “set pending NMIs”, “set and clear pending SVCs”, “set and clear pending SysTicks”, “check pending exceptions”, “check vector numbers of pending exceptions with the highest priority”, “and check vector numbers of active exceptions”.
Vector table offset register
Set the offset of the vector table in the vector table offset register.You can also check if the vector table is in RAM or code memory.
Application Interrupt and Reset Control Register
The application interrupt and reset control registers are used to “determine the endian format of data”, “clear active information when debugging or recovering from a hardware failure”, “reset the system”, and “change the priority grouping”.
system control register
The system control register is used for power management of the processor.
configuration control register
The configuration control registers are used for “Allowing Ignore Bus Fault for NMI, Hard Fault, and FAULTMASK”, “Trapping Division by 0 and Unaligned Access”, “Allowing User Access to Software Trigger Exception Register”, and “Controlling Entry to Thread Mode”.
system handler control and state register
The system handler control and status registers are used to “enable or disable the system handler”, to “determine the pending status of the bus fault, memory management fault, SVC”, and to “determine the active status of the system handler”.
system handler priority register
The system handler priority register is used to prioritize the system handlers of “Memory Management”, “Bus Fault”, “Usage Fault”, “Debug Monitor”, “SVC”, “SysTick”, and “PendSV”.
Configurable Fault Status Register
There are three configurable fault status registers.
- Memory Management Fault Status Register
- Bus Fault Status Register
- Usage Fault Status Register
These contain information about local faults.
Debug Fault Status Register
The Debug Fault Status Register is used to monitor “External Debug Request”, “Vector Catch”, “Data Watch Point Match”, “BKPT Instruction Execution”, and “HALT Request Content”.
Hard Fault Status Register
The Hard Fault Status register is used to control the events that activate the hard fault handler.
Memory Management Fault Address Register
The Memory Management Fault Address Register stores the address of the cause of the memory management fault.
Bus Fault Address Register
The Bus Fault Address Register stores the address at which the bus fault occurred.
Auxiliary Fault Status Register
The Auxiliary Fault Status Register is used to determine additional system fault information.
software trigger interrupt register
The software trigger interrupt register holds the interrupt that will trigger.