Control and identification registers
L1 Cache Control Register (CACR)
CACR controls the ECC and L1 cache consistency usage model for L1.
L1 cache identification register
The following table shows the list of identification registers.
|0xE000ED14||Configuration and Control Register (CCR)||Set or return structure and control data and manage caches and branch predictions.|
|0xE000ED78||Cache Level ID Register (CLIDR)||Indicates the cache level to be implemented. Architecturally, the number of cache levels for instructions and data can vary.|
|0xE000ED7C||Cache Type Register (CTR)||It provides information about the structure of the cache.|
|0xE000ED80||Cache Size ID Register (CCSIDR)||Provides information on the size and behavior of the selected instruction/data cache. Architecturally, up to eight levels of caching are possible. Includes instruction/data or unified caches; includes L1 instruction/data caches only|
|0xE000ED84||Cache Size Selection Register (CSSELR)||CSSELR chooses the current CCSIDR by specifying the following|
Point of Unification and Consistency
The point of unification (PoU) and point of coherency (PoC) concepts used in Cortex-A are also used in the Cortex-M7. However, the Cortex-M7 does not have built-in L2 cache or later, so if the microcontroller vendor does not have L2 cache or later, the relationship between the L1 cache and system memory (e.g., built-in Flash and SRAM) is the target.
Point of unification (PoU)
Point of unification (PoU) for the processor ensures that the instruction and data caches see the same copy of the memory location; in Cortex-A, the L2 integrated cache (a cache containing both instructions and data) is a given. The PoU is a single-processor memory system that combines instruction and data caches.
Point of coherency (PoC)
For a specific Modified Virtual Address (MVA), the Point of Coherency (PoC) ensures that all agents with access to memory will see the same copy of the memory location In the Cortex-M7, this is also the main system memory. Here, an agent is software that acts as a proxy or intermediary for the user or other software. Or software that works on behalf of the user.
Cash Maintenance Operation Register
All cache maintenance operations are performed using the registers in the table below. They are located in the memory-mapped System Control Space (SCS) space in the internal PPB memory space. Cache maintenance operations can only be loaded/stored in privileged mode, performing them in non-privileged mode will cause a BusFault.
|0xE000EF50||ICIALLU||Disable all instruction caches|
|0xE000EF58||ICIMVAU||Disabling Instruction Caching by Address to PoU|
|0xE000EF5C||DCIMVAC||Disabling data caching by address to PoC|
|0xE000EF60||DCISW||Set and disable data caches, specifying a way|
|0xE000EF64||DCCMVAU||Data cache cleaning by address to PoU|
|0xE000EF68||DCCMVAC||Data cache cleaning by addressing to PoC|
|0xE000EF6C||DCCSW||Cleaned by specifying a set and way of data cache|
|0xE000EF70||DCCIMVAC||Data cache cleaning and deactivation by address to PoC|
|0xE000EF74||DCCISW||Clean and deactivate a set of data caches, specifying ways to clean and deactivate|
Cache Maintenance Instructions
(1) Data synchronization barrier (DSB) instruction
The DSB acts as a special data synchronization memory barrier. It places the processor in a wait state to prevent subsequent instructions from being executed until all memory accesses prior to this instruction have been completed. Thus, all previous cache maintenance operations are guaranteed to complete.
(2)Instruction synchronization barrier (ISB) instruction
ISB acts as an instruction synchronization barrier. This causes the processor’s pipeline to be discarded. Therefore, instructions after ISB are retrieved from the cache or memory again after ISB is completed. This ensures that instruction cache maintenance operations are visible for subsequent “instruction fetching”. (See Write Buffer and Barrier Instructions (Cortex-A, Part 11))
Initialization and Enablement
Initializing and enabling the cache
On power-on reset, they must be completely disabled once in software before enabling the instruction and data caches. The cache line enable bit is held in the tag (in the cache RAM). Failure to do so will cause an unpredictable phenomenon. Also, in the case of a software reset, if the contents of the cache at the time of the reset are trustworthy, no invalidation is necessary.
Invalidate the entire data cache
The software can use the following sample code to disable the entire data cache. The operation is performed repeatedly on individual lines of the cache. Line invalidation is done by using the DCISW register in the Private Peripheral Bus (PPB) memory area. The number of ways and sets of caches is determined by reading the CCSIDR register.
CCSIDR EQU 0xE000ED80 CSSELR EQU 0xE000ED84 DCISW EQU 0xE000EF60 MOV r0, #0x0 LDR r11, =CSSELR STR r0, [r11] ; Select Data Cache size DSB LDR r11, =CCSIDR LDR r2, [r11] ; Cache size identification AND r1, r2, #0x7 ; Number of words in a cache line ADD r7, r1, #0x4 MOV r1, #0x3ff ANDS r4, r1, r2, LSR #3 MOV r1, #0x7fff ANDS r2, r1, r2, LSR #13 CLZ r6, r4 LDR r11, =DCISW inv_loop1 MOV r1, r4 inv_loop2 LSL r3, r1, r6 LSL r8, r2, r7 ORRr 3, r3, r8 STR r3, [r11] ; Invalidate D-cache line SUBS r1, r1, #0x1 BGE inv_loop2 SUBS r2, r2, #0x1 BGE inv_loop1 DSB ISB
Disable instruction cache
Disabling the instruction cache can be done with the following example code. The operation is done by writing to the ICIALLU register in the PPB memory area.
ICIALLU EQU 0xE000EF50 MOV r0, #0x0 LDR r11, =ICIALLU STR r0, [r11] DSB ISB
Enabling Data and Instruction Caching
The data cache and instruction cache can be enabled after initialization using the following sample code. The operation is performed by modifying the CCR.IC and CCR.DC fields in the PPB memory area.
CCR EQU 0xE000ED14 LDR r11, =CCR LDR r0, [r11] ORR r0, r0, #0x1:SHL:16 ; Set CCR.DC field ORR r0, r0, #0x1:SHL:17 ; Set CCR.IC field STR r0, [r11] DSB ISB
Memory types and attributes
The Arm processor defines three types of memory and must be configured for each application. MPU is used to set the memory type. (By the way, Cortex-M7 and Cortex-R are set up in MPU, and Cortex-A is set up in MMU.
See the chapter “Memory Types and Access Orders (See Cortex-A, Part 10)” for more information on Cortex memory types.
The processor can be reordered for efficiency. It can also perform speculative reads.
Device and Strongly-ordered
By defining memory regions into either Device or Strongly-ordered memories, the processor protects the order of other operations associated with these memories. This means that you can buffer writes to memory. However, you cannot buffer writes to Strongly-ordered memory.
A memory system provides data synchronization between multiple bus masters in a system. Strongly-ordered memory is always shareable. If multiple bus masters have access to a memory area that is not shareable, the user must ensure data consistency between the bus masters in software.
Execute Never (XN)
This means that the processor prevents instruction access; executing an instruction from the XN region results in an exception fault.