Cortex-M3 Overview

About the Processor

Generally speaking, a processor refers to an arithmetic unit and a control unit that are combined into a single unit.(Different people may define the processor differently…)

The Cortex-M3 also includes the control and arithmetic parts, which we call the Cortex-M3 processor.The Cortex-M3 processor contains the Cortex-M3 core, which is the arithmetic part of the Cortex-M3 processor, so it can be said that the Cortex-M3 processor and Cortex-M3 core have a two-layered structure.

Cortex-M3 Core

The Cortex-M3 core is the so-called CPU part.The main circuit is a 32-bit ALU (Arithmetic Logical Unit).This includes the hardware division and multiplication circuits.

Although not shown in the figure below, it also has a barrel shifter, which can shift many bits at a time.In addition to the arithmetic circuitry, the instruction decoder is included to decipher the instructions fetched from the instruction interface.And then there are the control circuits that control these.

The interrupt circuit NVIC is not included in the Cortex-M3 core.Only the interface circuitry is included, and the body of the NVIC is outside the Cortex-M3 core.ETMs for debugging circuits are also not included in the Cortex-M3 core.This is also an interface circuit and is mounted outside the Cortex-M3 core.

Other circuits include a data interface to move data in and out.

Cortex-M3 processor

The main part of the Cortex-M3 processor is the Cortex-M3 core.Closely related to the Cortex-M3 core is the Nested Vectored Interrupt Controller (NVIC).It single-handedly handles exceptions (interrupts and faults).

The debugging circuitry includes an ETM for instruction tracing and a Serial Wire Viewer (SWV) for data tracing.The ETM is optional, but the SWV is standard equipment.

As for the debugging circuit, the Cortex-M3 processor itself does not have a JTAG (Joint Test Action Group).It is located outside of the Cortex-M3 and its interface is handled by the DAP (Debug Access Port).

A memory protection unit (MPU) is also an option.When the user accesses the protected memory area, fault processing is performed.The hardware associated with the MPU is a data watchpoint and a Flash patch.

There is a bus matrix in the Cortex-M3 processor that allows easy and fast access to data.The bus matrix also makes it easy to process bit-wise data.The circuitry associated with the bus matrix is a code interface and an SRAM & peripheral interface. Both of them manage and control memory access.

barrel shifter

A barrel shifter is a piece of hardware that shifts many bits at a time.It was not often installed in old microcomputers because the logic circuit was too large and cost was increased.However, many recent microcomputers with finer processes have come standard with them.