Core registers, interrupts and exception handling

core register

The core register configuration of the Cortex-M7 is the same as that of the Cortex-M3/M4. (See Cortex-M, Part 11.)

13 general-purpose registers R0 to R12

It is used for data processing and indirect addressing.

Stack pointer (SP) R13

This shows the location of the stack, with the bank switching between the SP process (PSP) and the SP main (MSP).

Link register (LR) R14

If the subroutine (function is called), the return address is entered.

Program counter (PC) R15

The address of the instruction that is currently being executed.

Program Status Register (xPSR)

The state of the Cortex-M7 is shown here. The interior is divided into three parts.The application PSR indicates the state of the operation result (zero, negative value, etc.), the interrupt PSR indicates the state of the interrupt, and the execution PSR indicates the state of the execution of the Thumb-2 instruction.

Priority Mask Register (PRIMASK)

The PRIMASK register masks all exceptions according to a configurable priority.

Fault mask register (FAULTMASK)

The FAULTMASK register masks all exceptions, except for Non Maskable Interrupt (NMI).

Base Priority Mask Register (BASEPRI)

The BASEPRI register defines a minimum priority for exception handling.When BASEPRI is set to a non-zero value, it masks all exceptions as BASEPRI values, depending on the same or lower priority.

Control register (CONTROL)

The control registers control the stack and privilege levels used for software execution.

Interrupts and exception handling

Overview

The Cortex-M7, like the Cortex-M3/M4, features NVIC: Nested Vectored Interrupt Controller, which is the same as the Cortex-M3/M4.Interrupt handling has been optimized for low overhead and interrupt performance.

For example, auto-save and auto-restore contexts, late arrival, tail-chains, and instructional fetches in parallel with saving contexts.See “Cortex-M Volume 15” for more information on tail chaining, late arrival, and usurpation.

The Cortex-M7 has an interrupt overhead of 12 cycles, which assumes a zero-weighted memory system with TCM (Tightly Coupled Memory) and no cache hit by fetching from AXIM; using an FPU takes a few more cycles.(In addition to the normal stack operation, the S0 to S15 registers and the FPSCR are also stacked.)
The Cortex-M7 also controls the low power mode.

Nested Vectored Interrupt Controller features

• External interrupts can be set from 1 to 240.
  The specific allocation of interrupts is set by the implementation of the microcontroller vendor, so please check the specifications of each product.In many cases, it may be set to “reserve” in consideration of product deployment.
• The interrupt priority level can be set from 0 to 255.
  This, too, is set by the microcontroller vendor’s implementation, but there are few microcontrollers that can actually set an interrupt priority of 256 levels, and most products have a maximum of 16 levels.In addition, the interrupt priority can be changed by the software, so it can be changed on an ad-hoc basis. Please refer to “Cortex-M Part 16” for the specific setting method.
• Supports level and pulse detection
  The core itself supports both, but this too is set by the microcontroller vendor’s implementation.
• External NMI (Non-Maskable Interrupt) is supported.
• The wake-up interrupt controller (WIC) provides Utra-low power sleep mode support.
• The processor automatically stacks the state at the start of the exception handling and automatically fetches it from the stack at the end.Therefore, there is no overhead due to instruction execution. This provides exception handling with a short delay time.
• The user has full access to the NVIC from privileged mode, but can also withhold interrupts in user mode if Configuration and Control Register is allowed. Any other user mode access will cause a bus fault.
• All NVIC registers are word access only.

low power mode

• When WIC is implemented, Ultra-low power sleep mode support is enabled.WIC is a vendor option. Please check the specifications of the product to see if it is equipped.
• It allows the processor and NVIC to enter Utra-low power sleep mode, leaving it to the WIC to identify and prioritize interrupts.
• When the WIC is used, the user enables SLEEPDEEP in the system control register.
• The processor executes the WFI (Wait For Interrupt), WFE (Wait For Event), and SEV (Send Event) instructions.
• In addition, the processor also supports the use of SLEEPONEXIT.
  Then, when the exception handler returns to “thread mode”, it puts the processor core into sleep mode.

Level interrupts and pulse interrupts

• The processor supports both level and pulse interrupts.
  Again, the microcontroller vendor will decide whether to support it or not, so check the product specifications to see if it is supported or not.
• The level interrupt will remain asserted until cleared by the ISR accessing the device.
• A pulse interrupt is a type of edge model. The edges must be sampled on the rising edge of the Cortex-M7 clock rather than remaining asynchronous.
• In the case of level interrupts, if the signal is not de-asserted before returning from the interrupt routine, the interrupt will be re-holded and re-activated. This is especially useful in the case of FIFO and buffer-based devices.The reason for this is to ensure that those devices are drained by a single ISR or by repeated booting, without any extra work.This means that the device will hold the signal assertive until it is empty.
• A pulse interrupt can be reasserted during an ISR. As a result, the interrupt may be both pending and active at the same time.
  If another pulse arrives while the interrupt is still pending, the hold will continue, and the ISR can only be executed for one interrupt.Pulse interrupts are used for signals that occur at regular intervals or are repeated by external signals in most cases.

vector table

The vector table is essentially the same as the Cortex-M3/4. Contains the initial value of the stack pointer, the starting address, and the exception vector for the exception handler. If the LSB of each vector is 1, it indicates an exception handler for the Thumb code.

stack configuration

When using floating-point routines, the Cortex-M7 processor automatically stacks the floating-point state in addition to the normal stacking behavior when handling exceptions. Specifically, the 32-bit single-precision registers (S0-S31) and the FPSCR registers for status and configuration are stacked.

NVIC control using CMSIS

Here is an example of how to control NVIC using CMSIS.

投稿者

菅井 賢

国内外の半導体メーカーにおいて、マイコンの設計・開発・技術サポートに従事。2019年インスケイプ株式会社へ入社。APS初心者講座「Cortex-M編」の執筆をはじめ、豊富な経験と知識を活かし、初心者にもわかりやすい技術記事を提供している。

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