coprocessor

Coprocessor Overview

What is a co-processor?

When using an Arm processor (except for the Cortex-M series), you must understand the coprocessor registers because the coprocessor is responsible for setting up the cache of processor functions, MMU, etc. The coprocessor is not located in memory space and uses dedicated instructions to read and write. The advantage of not being located in memory space is that all 4G bytes of memory space can be used effectively. Some coprocessor registers can only be accessed in privileged mode, so please refer to your processor’s “Technical Reference Manual (*1)”.

• There are 16 coprocessors defined.
• The CP15 (Coprocessor 15) provides system control functions.
• The CP11 (co-processor 11) supports double precision floating point operations.
• The CP10 (co-processor 10) supports single precision floating point operations as well as extensions to both VFP advanced SIMD architectures.

(*1) The English version of “Cortex-A9 Technical Reference Manual Revision:r4p1” or the Japanese version “ See Cortex-A9 Technical Reference Manual Revision: r2p2“

Coprocessor Access Instructions

The coprocessor is accessed by the MRC/MCR instructions. There is a coprocessor register that can be accessed only in the privileged mode, so use it with caution.

MRC instruction

The MRC instruction performs a read from the coprocessor register to the processor register.

MRC{ cond } coproc,# opcode1,Rd,CRn,CRm {, # opcode2 }

MCR Instruction

The MCR instruction writes to the coprocessor register from the processor register.

MCR{ cond } coproc,#opcode1,Rd,CRn,CRm {, # opcode2 }

How to access the coprocessor

If you use the Arm compiler to access the coprocessor, create it in an inline assembly language or assembly language using the “__asm” keyword.

Example of accessing the coprocessor in the C/C++ compiler

If you use inline assembly language, you can write assembly instructions together with __asm{….} You can use __asm{…} for all of your assembly instructions.

void enable_caches( void )
{
  unsigned long reg;

__asm {
  MRC  p15,0,reg,c1,c0,0       // Reads the SCTLR (system control register)
  ORR  reg,reg,#(0x1 << 12)    // Allow instruction caching (SCTLR.I [12])
  ORR  reg,reg,#(0x1 <<  2)    // Allow data caching (SCTLR.D [2])
  ORR  reg,reg,#(0x1 << 11)    // Allow program flow prediction (SCTLR.Z [11])
  MCR  p15,0,reg,c1,c0,0       // Writing SCTLR
//==================================================================
// Allows Cortex-A9 data prefetching
//==================================================================
  MRC  p15,0,reg,c1,c0,1       // Reads the ACTLR (auxiliary control register)
  ORR  reg,reg,#(0x1 << 2)     // Enable data prefetch activation (ATRR.DP[2])
  MCR  p15,0,reg,c1,c0,1       //  Write the ACTLR
  }
}

Example of accessing the assembly language coprocessor

AAPCS (Procedure on Arm Architecture) It is possible to execute coprocessor access instructions as a function from C/C++ language by writing an assembly program according to the "Call Standard".

EXPORT enable_caches        ; allow cache and branch prediction

enable_caches  FUNCTION
  MRC  p15,0,r0,c1,c0,0     ; Read SCTLR
  ORR  r0,r0,#(0x1 << 12)   ; Allow instruction cache (SCTLR.I[12])
  ORR  r0,r0,#(0x1 <<  2)   ; Allow data caching. (SCTLR.D[2])
  ORR  r0,r0,#(0x1 << 11)   ; Allows program flow prediction. (SCTLR.Z[11])
  MCR  p15,0,r0,c1,c0,0     ; Write SCTLR
;==================================================================
; Allow data prefetching function
;==================================================================
  MRC  p15,0,r0,c1,c0,1     ; Read ACTLR
  ORR  r0,r0,#(0x1 << 2)    ; enable data prefetching (ATRR.DP[2])
  MCR  p15,0,r0,c1,c0,1     ; Write ACTLR
  BX   lr
  ENDFUNC

Coprocessor configuration example

When initializing the Cortex-A9 processor, you need to set up the coprocessor 15 (CP15). In this article, we will explain the following settings.

• Disable TLB (Transform Look-Aside Buffer) and Array of Branch Prediction
• Disable instruction/data cache
• VFP/NEON access rights and configuration
• Setting to change the vector address
• Setting up cache, MMU and branch predictions

Disabling TLBs and Branch Predictor Arrays

The TLB and branch predictor are not initialized at reset, so they are disabled at initialization.

【sample program】

;==================================================================
; Disabling TLBs and Branch Predictor Arrays
;==================================================================
  MOV   r0,#0               ; Set the initial value
  MCR   p15,0,r0,c8,c7,0    ; Total TLB disablement
  MCR   p15,0,r0,c7,c5,6    ; Branch Predictor Array Disabled		

TLBIALL (Global Disable Register)

• Disable the entire unified TLB, and if independent instruction TLBs and data TLBs are implemented, disable them simultaneously.
• The setting of the argument register <Rd> is ignored and can be executed in privileged mode only.

【Register Access Instructions】

MCR    p15,0,<Rd>,c8,c7,0   ; Writing a TLB-wide disablement

BPIALL (Branch Predictor Array Invalidator Register)

• Disable the entire branch predictor array.
• The setting of the argument register <Rd> is ignored and can be executed in privileged mode only.

【Register Access Instructions】

MCR    p15,0,<Rd>,c7,c5,6   ; Writing of Branch Predictor Array Disablement

Disabling instruction/data caches

The cache is not disabled on reset, so the L1 data cache and L1 instruction cache must be disabled. The data cache needs to be disabled for each line and way, so the information about the cache is obtained from CCSIDR (cache size identification register) and disabled.

【sample program】

  MOV   r0,#0                 ; Set to the default value.
  MCR   p15,0,r0,c7,c5,0      ; Disabling the entire instruction cache
;
; Disable the data cache.
;
  MOV  r10,#0                 ; Select Data Cache
  MCR  p15,2,r10,c0,c0,0      ; In the cache size selection register (CSSELR)
                              ; Select Data Cache
  ISB                         ; instruction-synchronous barrier instruction to re-fetch
  MRC  p15,1,r1,c0,c0,0       ; Read CCSIDR
  AND  r2,r1,#7               ; Get the cache line size (b001=8 words/line)
  ADD  r2,r2,#4               ; Find the number of shifts in the set number of DCISW registers.
  LDR  r4,=0x3FF              ; Set the maximum number of ways mask
  ANDS r4,r4,r1,LSR #3        ; Set the number of ways in the r4 register.
  CLZ  r5,r4                  ; Find the number of shifts of the way number in the DCISW register.
  LDR  r7,=0x7FFF             ; Set the set number mask setting.
  ANDS r7,r7,r1,LSR #13       ; Set the number of sets in the r7 register.
                              ; 0x7F=12Kbyte/0xFF=32Kbyte/0x1FF=64Kbyte
Loop2
  MOV  r9,r4                  ; Set the number of ways to the r9 register.
Loop3
  ORR  r11,r10,r9,LSL r5      ; Set the way number and cache number.
  ORR  r11,r11,r7,LSL r2      ; Set the set number
  MCR  p15,0,r11,c7,c6,2      ; by set/way in DCISW register
                              ; Disabling the data cache line
  SUBS r9,r9,#1               ; Way number -1
  BGE  Loop3                  ; Initialize each way.
  SUBS r7,r7,#1               ; Set the set number to -1
  BGE  Loop2                  ; initialize each set

ICIALLU (instruction cache-wide invalidation register)

• Disable all instruction caches and flush the branch destination cache.
• argument register<Rd>setting is ignored and can only be executed in privileged mode.

【Register Access Instructions】

MCR    p15,0,<Rd>,c7,c5,0   ; ICIALLU writes

CSSELR (Cache size selection register)

• Used to select the CCSIDR.
• You can read and write in privileged mode only.

【Register Access Instructions】

MCR p15,2,<Rd>,c0,c0,0       ; Loading CSSELR
MCR p15,2,<Rd>,c0,c0,0       ; CSSELR writing

【register format】

CCSIDR (Cache Size Identification Register)

• Provides information about the architecture of the cache.
• CCSIDR is implemented for each cache accessible by the processor.
• In CSSELR, select CCSIDR.
• You can read it in privileged mode only.

【Register Access Instructions】

MRC   p15,1,<Rd>,c0,c0,0      ; CCSIDR Reading

【register format】

• When the instruction cache value is read, the [31:28] bit is 0b0010.
• When the data cache value is read, the [31:28] bit is 0b0111.

DCISW (data cache invalidation register) by set/way

• Disable the data cache lines set by the set/way.
• You can write in privileged mode only.

【Register Access Instructions】

MCR    p15,0,<Rd>,c7,c6,2   ; Writing data cache invalidation by set/way

【Cortex-A9 register format】

DCCSW (Data Cache Cleaning Register) by set/way

• Clean the data cache line by set/way.
• You can write in privileged mode only.

【Register Access Instructions】

MCR p15,0,<Rd>,c10,c6,2 ; Writing a clean data cache by set/way

【Cortex-A9 register format】

VFP/NEON access rights and uptime settings

At reset, the VFP/NEON access is initialized to the prohibited and non-operational state, so it is necessary to set the access privileges in the initialization process and set it to the operational state.
In the sample program, the coprocessor 10 (CP10) and coprocessor 11 (CP11) are set up for full access, and the advanced SIMD extension and VFP extension are set up for operation.

【sample program】

;=====================================================================
; NEON/VFP access permissions
; CP10/CP11 full access settings
;=====================================================================
   MRC   p15,0,r0,c1,c0,2   ; Read CPACR
   ORR   r0,r0,#(0xF << 20) ; CP10/CP11 full access configuration
   MCR   p15,0,r0,c1,c0,2   ; Write CPACR
   ISB                      ; re-fetch with instruction synchronization barriers
;=====================================================================
; Start to NEON the VFP.
;=====================================================================
  MOV   r0,#0x40000000      ;
  VMSR FPEXC,r0             ; Write EN bit in the floating-point exception register

Coprocessor Access Control Register (CPACR)

• Set up access permissions to the coprocessors CP10 and CP11 and set up advanced SIMD extensions and register access restrictions for the VFP registers.
• You can read and write in privileged mode only.

【Register Access Instructions】

MRC p15,0,<Rd>,c1,c0,2 ; CPACR reading
MCR p15,0,<Rd>,c1,c0,2 ; CPACR writing

【register format】

FPEXC (Floating Point Exception Register)

• FPEXC provides global enable/disable control of advanced SIMD and VFP extensions.

【Register Access Instructions】

VMRS { cond } Rd, extsysreg   ; Reading the Arm register from the NEON/VFP register
VMSR { cond } extsysreg , Rd  ; Writing the NEON/VFP register from the Arm register

【register format】

Setting to change the vector address

The exception vector address can be changed by setting an address in the VBAR (vector-based register).
If the V bit of SCTLR is 1, remapping by VBAR is not possible.

【sample program】

;===================================================================
; Use VBAR to change vector addresses
;===================================================================
  LDR    r0,=Vectors                  ; Set the first address of the vector
  MCR    p15,0,r0,c12,c0,0            ; Writing to VBAR

VBAR

• When the security extensions are implemented and no high-level exception vector is selected, the vector-based address register (VBAR) provides an exception base dress for exceptions that are not handled in monitor mode.
• The high-level exception vector always has a base dress of 0xFFFF_0000 and is not affected by the vector base address register.
• You can read and write in privileged mode only.

【Register Access Instructions】

MRC p15,0,<Rd>,c12,c0,0 ; VBAR loading
MCR p15,0,<Rd>,c12,c0,0 ; VBAR writing

【register format】

Operation settings for cache, MMU and branch prediction

You need to configure the cache and MMU (see Part 12) in the SCTLR.

【sample program】

  MRC   p15,0,r0,c1,c0,0    ; Read SCTLR
  ORR   r0,r0,#(0x1 << 12)  ; Run instruction quiche (SCTLR.I [12])
  ORR   r0,r0,#(0x1 <<  2)  ; run data quiche (SCTLR.D [2])
  ORR   r0,r0,#(0x1 << 11)  ; run program flow prediction (SCTLR.Z [11])
  ORR   r0,r0,#(0x1 <<  0)  ; Running MMU (SCTLR.M [0])
  MCR   p15,0,r0,c1,c0,0    ; Write SCTLR
;==================================================================
; Allows the data prefetching function.
;==================================================================
  MRC   p15,0,r0,c1,c0,1    ; Read ACTLR
  ORR   r0,r0,#(0x1 << 2)   ; run data prefetch (ATRR.DP[2])
  MCR   p15,0,r0,c1,c0,1    ; Write ACTLR

SCTLR

Configure various processor settings such as cache and MMU.

Read/write in privileged mode only.

【Register Access Instructions】

MRC p15,0,<Rd>,c1,c0,0 ; SCTLR reading.
MCR p15,0,<Rd>,c1,c0,0 ; SCTLR writing.

【register format】

ACTLR

Read/write in privileged mode only.

【Register Access Instructions】

MRC p15,0,<Rd>,c1,c0,1 ; ACTLR reading
MCR p15,0,<Rd>,c1,c0,1 ; ACTLR writing

【register format】

In this article, I've focused on the coprocessors that need to be set up when you initialize them. In normal programming, you're unlikely to have access to them (laughs), but there are some registers that can help you solve problems when an exception occurs, so I recommend reading the manual.

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