Overview of the cache
A cache is a small, fast memory that sits between the large, slow main memory and the processor. The cache copies some frequently accessed “instructions” or “data” and allows the processor to access them at high speed, thereby increasing the speed of program execution. In general, when the required data is present in the cache, it is called a “cache hit” and when the required data is not present in the cache, it is called a “cache miss”.
Points to keep in mind when using cache
When using the cache, the following settings are required
- MMU (referring to the 12th) or memory type (Refer to Part 10) in the MPU (Memory Protection Unit).
- The Cortex-A9 must be disabled after resetting and before the cache can be enabled.
If you use a cache, you can increase the speed of your program’s execution, but the program’s execution time will vary depending on the cache’s hit rate.
Arm processor with built-in cache
The Cortex-A processor supports multiple levels of caching.
- The L1 cache is integrated into the processor and contains instruction and data caches.
- Most of the L2 cache is included as a unified cache (*1).
(*1)Instruction and data are not separated and are managed in the same cache memory area.
Cache structure and behavior
Let’s take a 32-Kbyte L1 4-Way data cache as an example to illustrate the structure.
- The line (line 0 to line 255) is 8 words.
- An updated (Dirty) bit in the line, indicating that the line has been modified by the processor.
- line indicates a valid (valid) state.
When the address 0x1000_0100 is accessed, the cache does the following
- At addresses Bit 12 to Bit 5, select the line, so select “Line 8” (0x08).
- Way is automatically selected by the Victim Counter.
- tag, addresses Bit 31 to Bit 13 are stored.
- Saves data (8 words) from 0x1000_0100 to 0x1000_011F on the line.
Maintaining the cache
We do not normally perform cache maintenance, but you should be careful if you do.
Clearing the Valid bit of the cache line will invalidate all data held in the cache.
Reflects the updated (Dirty) cache lines to external memory, so that the contents of the cache and external memory match.
Mode of operation of data cache
The data cache can be configured for write-back and write-through modes of operation.
Only the data cache is updated, not the memory.
Update the data cache and memory.
Read Allocation Action
When the processor core executes a read instruction, it reads from memory to the cache in line size units. The address to start reading is the line size unit boundary; for Cortex-A9, the cache line size is 32 bytes (8 words).
Right Allocation Action
When the processor core executes a write instruction, it reads from memory to the cache in line size units and then writes. The address to start reading is the line size unit boundary; for Cortex-A9, the cache line size is 32 bytes (8 words).
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